A 1.8 V 3.2 /spl mu/W comparator for use in a CMOS imager column-level single-slope ADC

Snoeij, MF; Theuwissen, A.J.P.A.M.; Huijsing, J.H.

A 1.8 V 3.2 /spl mu/W comparator for use in a CMOS imager column-level single-slope ADC

Conference paper (2005)

Authors

MF Snoeij Electronic Instrumentation -

A.J.P.A.M. Theuwissen Electronic Instrumentation -

J.H. Huijsing Electronic Instrumentation -

Research Group

Electronic Instrumentation () (TU Delft)

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Published Date

2005

Language

English

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Faculty

Electrical Engineering, Mathematics and Computer Science

Department

Microelectronics

Research Group

Electronic Instrumentation

Abstract

In this paper, a 1.8 V 3.2 /spl mu/W comparator is presented. It features a hybrid offset compensation scheme and achieves over 60 dB gain with an input offset below 150 /spl mu/V. The comparator is designed in a 0.18 /spl mu/m CMOS process and is specifically designed to be used as the key component of a column-level single-slope ADC of a CMOS imager. This ADC architecture is attractive because of its low noise, but so far this has come at the price of a relatively high power consumption. Using this comparator design, the power consumption of column-level single-slope ADC can be reduced significantly.