Multilayer VLSI layout for interconnection networks

Conference paper (2000)

Authors

CH Yeh External organisation
EA Varvarigos Computer Engineering - EEMCS
B Parhami External organisation
Research Group
Computer Engineering (EEMCS) (TU Delft)
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Published Date

2000

Language

Undefined/Unknown

Reuse Rights

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Faculty

Electrical Engineering, Mathematics and Computer Science

Department

Quantum & Computer Engineering

Research Group

Computer Engineering