Resilient chip multiprocessors with mixed-grained reconfigurability

Journal article (2016)

Authors

Ioannis Sourdis Chalmers University of Technology

Danish Anis Khan Chalmers University of Technology

Alirad Malek Chalmers University of Technology

Stavros Tzilis Chalmers University of Technology

Georgios Smaragdos Erasmus MC

C. Strydis Erasmus MC

Affiliation

External organisation

Reliability Multicore Availability CMP Serviceability Reconfigurable hardware Adaptable architectures Microarchitecture implementation considerations Pipeline implementation Single-chip multiprocessor

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Published Date

2016

Language

English

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Abstract

This article presents a chip multiprocessor (CMP) design that mixes coarse- and fine-grained reconfigurability to increase core availability of safety-critical embedded systems in the presence of hard errors. The authors conducted a comprehensive design-space exploration to identify the granularity mixes that maximize CMP fault tolerance and minimize performance and energy overheads. The authors added fine-grained reconfigurable logic to a coarse-grained sparing approach. Their resulting design can tolerate 3 times more hard errors than core redundancy and 1.5 times more than any other purely coarse-grained solution.