The TM3270 media-processor data cache

Conference paper (2005)

Authors

JW van de Waerdt Computer Engineering - EEMCS
S Vassiliadis Computer Engineering - EEMCS
JP van Itegem External organisation
H van Antwerpen External organisation
Research Group
Computer Engineering (EEMCS) (TU Delft)
More Info
expand_more

Published Date

2005

Language

Undefined/Unknown

Reuse Rights

Other than for strictly personal use, it is not permitted to download, forward or distribute the text or part of it, without the consent of the author(s) and/or copyright holder(s), unless the work is under an open content license such as Creative Commons.

Faculty

Electrical Engineering, Mathematics and Computer Science

Department

Quantum & Computer Engineering

Research Group

Computer Engineering

Abstract

This paper describes the (micro-) architecture of the TM3270 data cache. We present the cache parameters, such as cache size, associativity, line size and cache policies. We describe the data cache pipeline partitioning and the cache memory structure organization. We introduce "collapsed" and "twoslot" load operations. Furthermore, we introduce a combined software/hardware based technique for prefetching of data into the cache. We use an MPEG2 encoder application for a quantative evaluation of architectural aspects such as data prefetching and show that MPEG2 encoding at 352*288 resolution (CIF) at 25 frames per second can be performed in 33.3 MHz.