Wrapper design for the reuse of a bus, network-on-chip, or other functional interconnects at test access mechanism

Journal article (2007)

Authors

A Amory External organisation
K.G.W. Goossens Computer Engineering - EEMCS
E Marinissen External organisation
M Lubaszewski External organisation
F Moraes External organisation
Research Group
Computer Engineering (EEMCS) (TU Delft)
More Info
expand_more

Published Date

2007

Language

Undefined/Unknown

Reuse Rights

Other than for strictly personal use, it is not permitted to download, forward or distribute the text or part of it, without the consent of the author(s) and/or copyright holder(s), unless the work is under an open content license such as Creative Commons.

Faculty

Electrical Engineering, Mathematics and Computer Science

Department

Quantum & Computer Engineering

Research Group

Computer Engineering