System and circuit level power modeling of energy-efficient 3D-stacked wide I/O DRAMs

Conference paper (2013)

Authors

K. Chandrasekar Computer Engineering
C Weis External organisation
Benny Akesson External organisation
N Wehn External organisation
K.G.W. Goossens Computer Engineering
Research Group
Computer Engineering
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Published Date

2013

Language

English

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Research Group

Computer Engineering

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