FPGA accelerated trading data compression

Master thesis (2020)

Authors

J. Chen Electrical Engineering, Mathematics and Computer Science

Contributors

M. Zaid (mentor)
F. Sebastiano (OLD)Applied Quantum Architectures (graduation committee member)
H.P. Hofstee (coach)
Maurice Daverveldt Optiver (coach)
Faculty
Electrical Engineering, Mathematics and Computer Science, Electrical Engineering, Mathematics and Computer Science
Copyright: © 2020 J. Chen
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Published Date

26-06-2020

Language

English

Reuse Rights

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Faculty

Electrical Engineering, Mathematics and Computer Science

Files

Msc_thesis_Jianyu_Chen_2.pdf
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