Exponential extended flash time-to-digital converter

Conference paper (2016)

Authors

Peng Chen University College Dublin
R.B. Staszewski University College Dublin
Affiliation
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Published Date

20-10-2016

Language

English

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Abstract

The digital-to-time converter (DTC)-based all-digital phase locked loop (ADPLL) attracts more and more attention due to its ultra-lower power consumption characteristic [1]. With DTC, the time-to-digital converter's (TDC) requirements are relaxed, not only for its range but also for its nonlinearity. However, the shortened TDC range, which is less than one digital controlled oscillator (DCO) output period in the new architecture makes the settling time longer and the TDC gain calibration difficult. This work introduces a technique to extend the TDC range by 16 times to accelerate the settling process, while the extended part can be disabled when ADPLL is in lock. Furthermore, the TDC gain calibration is easier.