FASTER run-time reconfiguration management

Conference paper (2013)

Authors

C.B. Ciobanu Chalmers University of Technology

D. Pnevmatikatos Foundation for Research and Technology - Hellas (FORTH)

K. Papadimitriou Foundation for Research and Technology - Hellas (FORTH)

G. Gaydadjiev Chalmers University of Technology

Affiliation

External organisation

FPGA Partial reconfiguration Run-time system manager

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Published Date

2013

Language

English

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Affiliation

External organisation

Abstract

The FASTER project Run-Time System Manager offloads programmers from low-level operations by performing task placement, scheduling, and dynamic FPGA reconfiguration. It also manages device fragmentation, configuration caching, pre-fetching and reuse, bitstream compression, and optimizes the system thermal and power footprints. We propose a micro-reconfiguration aware, configuration content agnostic ISA interface and a technology independent Task Configuration Microcode format targeting Maxeler Data Flow computers and Xilinx XUPV5 platforms. We achieve improved resource utilization with negligible performance overhead. Up to 4Gbps for DMA transfers, and up to 3Gbps for FPGA reconfiguration on Xilinx Virtex-5/6 devices is achieved.