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Implementing and evaluating a simplified transistor model for timing analysis of integrated circuitsZheng, X.Y. (author)Static Timing Analysis (STA) is one approach to verify the timing of a digital circuit. The currently used Gate Level Model (GLM) has limitations on performing STA for circuits when taking process variations into consideration. The transistor level model is developed taking the statistical factors into account. This thesis presents an...master thesis 2012