A Low-Spur Fractional-N PLL Based on a Time-Mode Arithmetic Unit

Gao, Z.; He, J.; Fritz, Martin; Shen, Y.; Zong, Z.; Spalink, Gerd; Alavi, S.M.; Staszewski, R.B.; Babaie, M.

doi:10.1109/JSSC.2022.3209338

A Low-Spur Fractional-N PLL Based on a Time-Mode Arithmetic Unit

Title

A Low-Spur Fractional-N PLL Based on a Time-Mode Arithmetic Unit

Author

Gao, Z. (TU Delft Electronics)
He, J. (TU Delft Electronics)
Fritz, Martin (Sony Europe Limited, Germany)
Shen, Y. (TU Delft Electronics)
Zong, Z. (TU Delft Electronics)
Spalink, Gerd (Sony Europe Limited, Germany)
Alavi, S.M. (TU Delft Electronics)
Staszewski, R.B. (TU Delft Electronics)
Babaie, M. (TU Delft Electronics)

Date

2023

Abstract

This article introduces a low-jitter low-spur fractional-N phase-locked loop (PLL) adopting a new concept of a time-mode arithmetic unit (TAU) for phase error extraction. The TAU is a time-signal processor that calculates the weighted sum of input time offsets. It processes two inputs - the period of a digitally controlled oscillator (DCO) and the instantaneous time offset between the DCO and reference clock edges - and then extracts the DCO phase error by calculating their weighted sum. The prototype, implemented in 40-nm CMOS, achieves 182-fs rms jitter with 3.5-mW power consumption. In a near-integer channel, it shows the worst fractional spur below -59 dBc. Under considerable supply or temperature variations, the worst spur still remains below -51.7 dBc without any background calibration tracking.

Subject

Arithmetic
Capacitors
Clocks
Digital-to-time converter (DTC)
fractional spur
Microelectronics
Phase locked loops
phase-locked loop (PLL)
process voltage and temperature (PVT)
Switches
time-mode arithmetic unit (TAU)
Voltage