Adaptive Clock Scheduling for Pipelined Structures

Adaptive Clock Scheduling for Pipelined Structures

Kuiper, B.

Cotofana, S.D. (mentor)

Electrical Engineering, Mathematics and Computer Science

Microelectronics & Computer Engineering

2009-08-26

With the advance of fabrication technology into the deep sub-micron era process parameter variations, temperature, and voltage fluctuations start to induce large variations into the delay of integrated circuits. The smaller the feature size the larger the variations become, and thus also their influence on the critical path delay of a logic stage in a pipelined structure. Traditionally, the critical path delay variations are dealt with by augmenting the critical path delay with a safety margin (over design) that is large enough to cover the worst case scenario. Due to the increasing variability the performance gap between this worst-case clocking method and the potential performance is increasing resulting into a massive underutilization of the technology. This thesis introduces a design for variability for pipelined structures called Adaptive Inverter Chain Based Pipeline (AICBP). It can observe and compensate for delay variations in pipelined structures. The main idea is to expose the data and the clock to the same variations such that the clocking of the registers is adapted to the delay of the logic. This results in a substantial reduction of the over design thus on a better utilization of the technology potential performance. Besides the hardware which can compensate for delay variations, the AICBP design also includes a number of smart mechanisms which can resolve timing errors and improve performance. The area overhead of the AICBP design is relatively small in comparison to other state-of-the-art proposals, since it does not require the augmentation of circuitry at the flip-flop level as is the case with some designs for variability. Some high level simulations have been done and these indicate an up to 46% performance improvement. However, this performance improvement depends heavily on the specific delay variations and the properties of the combinatorial logic. Two extensions to the basic AICBP design are presented in this thesis as well. One of these includes an advanced recovery mechanism and the other focuses on data dependent delay compensation techniques. These extensions allow the performance to be improved, but the cost in terms of area and also power is quite high.

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Student theses

master thesis

(c) 2009 Kuiper, B.